PLDs
With Galep5 it is mandatory that external DC supply is connected during PLD actions.
GAL
GALEP-4 is able to program GALs (Gate Array Logic) as made available by manufacturers such as Lattice, National Semiconductor, or SGS. Using GALs allows you to program customized logic circuits.
Three categories of GAL types practically replace all standard PALs.
Whenever a GAL is chosen rather than a memory module, the buffer window shows the Fuse-Map Hex data for that selected GAL. In the Options dialog you can then enter the settings for the fuse data, the signature (UES User Electronic Signature), and the Security Fuse.
The User-Signature allows for a short marking of the device; it can be directly entered in ASCII.
The Security-Bit, if set, prevents reading out the GAL. It can be reset only by completely deleting (erasing) the module.
Please Note: in the current programming specifications < Master Bit > and < programming counter > are not supported, even with older GAL types (A- and Standard-Type).
EPLDs from ATMEL (ATFs)
With regard to selected options in the Options dialog, generally the same options will be available for ATMEL ATF-EPLD's as are available for GALs.
We note that the Types ATF16LV8C and ATF16V8C will be the only exceptions to this general rule. These modules feature two operational modes:
1.Standard - Mode
2.Extended - Mode
1.:
In the Standard - Mode the ATF type is compatible with the common 16V8Jedec file with fuses from 0 to 2193. The Power-Down and the Sleep Modes respectively cannot be set via the software and are always disabled. In this case devices of the type ATF16LV8C or ATF16V8C should be chosen.
2.:
For the Extended - Mode types, ATF16LV8CEXT or ATF16V8CEXT must be used. When in extended mode therefore, the sleep mode is enabled/disabled with the additional fuse 2194. Please note the following:
Fuse 2194 = 0: Sleep-Mode disabled,
Fuse 2194 = 1: Sleep-Mode enabled.
For further details please refer to the documentation from ATMEL, or your development tool's documentation.
ATF750C/CL/LVC/LVCL
I. Prog. Mode ATF750C/CL/LVC/LVCL(V750):
Uses V750 type jedec file.
No UES, PD, PPK and Security fuses in jedec file.
PD and PPK fuses are programmed to 0(disabled).
Security fuse is not programmed (the security value in options menue don't have any effect).
Configuration fuses #14395 to #14434 are programmed to 0.
UES fuse bits are programmed to 0 and will not read or verified in this mode.
II. Prog. Mode ATF750C/CL/LVC/LVCL(V750B):
Uses V750B type jedec file.
No UES, PD, PPK fuse in jedec file.
PD and PPK fuses are programmed to 0(disabled).
UES fuse bits are programmed to 0 and will not read or verified in this mode.
Security fuse is set if enabled in options menue.
III. Prog. Mode ATF750C/CL/LVC/LVCL:
Uses F750C type jedec file.
Security fuse is set if enabled in options menue.
PD fuse is programmed to 0(disabled).
UES and PPK fuse values found in jedec file are programmed and verified.
Reserved fuse bits #14501 to #14503 are not programmed or verified and buffer will be set to 0 when reading the device.
IV. Prog. Mode ATF750CEXT/LVCEXT:
Uses F750C type jedec file.
Security fuse is set if enabled in options menue.
UES, PD and PPK fuse values found in jedec file are programmed and verified.
Reserved fuse bits #14501 to #14503 are not programmed or verified and buffer will be set to 0 when reading the device.
Not every ATF750 device can be programmend in this mode. An error message “Incorrect GAL Type” will be shown.
Programming with a separate verify call in modes I. to III. could cause a verify error. The case is that UES, PD and PPK fuses are not equal 0 in buffer but are programmed to 0 in this modes.
PALCE from AMD
cf. GALs!